1. Technical Field
Various embodiments relate to a semiconductor integrated circuit, and more particularly, to a semiconductor memory apparatus.
2. Related Art
A semiconductor memory apparatus is configured to store inputted data and output stored data. In a semiconductor memory apparatus, regions where data are stored are referred to as banks. A semiconductor memory apparatus is configured to include a plurality of banks.
A semiconductor memory apparatus is constituted by a large number of transistors, and a bank is constituted by transistors as well. The transistors react sensitively to a temperature variation. For example, the threshold voltage of a transistor rises as a temperature rises, and the threshold voltage of a transistor falls as a temperature falls.
A voltage level required to turn on a transistor rises as the threshold voltage of the transistor rises, and a voltage level required to turn on a transistor falls as the threshold voltage of the transistor falls.
Therefore, since a voltage level to turn on a transistor rises as a temperature rises, a turn-on timing of the transistor becomes late, and, since a voltage level to turn on a transistor falls as a temperature falls, a turn-on timing of the transistor becomes early.
If turn-on timings of transistors change according a temperature, the response characteristics of a semiconductor memory apparatus constituted by transistors change as well.
Referring to FIG. 1, a conventional semiconductor memory apparatus includes first to fourth banks 10 to 40, and a signal transfer block 50.
The first bank 10 operates in response to a first command signal CMD_1.
The second bank 20 operates in response to a second command signal CMD_2.
The third bank 30 operates in response to a third command signal CMD_3.
The fourth bank 40 operates in response to a fourth command signal CMD_4.
The signal transfer block 50 outputs an internal command signal CMD_internal as one signal of the first to fourth command signals CMD_1 to CMD_4 in response to first and second bank select signals BANK_sel<0:1>. For example, the signal transfer block 50 outputs the internal command signal CMD_internal as the first command signal CMD_1 in the case where both the first and second bank select signals BANK_sel<0:1> are low levels. The signal transfer block 50 outputs the internal command signal CMD_internal as the second command signal CMD_2 in the case where the first bank select signal BANK_sel<0> is a high level and the second bank select signal BANK_sel<1> is the low level. The signal transfer block 50 outputs the internal command signal CMD_internal as the third command signal CMD_3 in the case where the first bank select signal BANK_sel<0> is the low level and the second bank select signal BANK_sel<1> is a high low level. The signal transfer block 50 outputs the internal command signal CMD_internal as the fourth command signal CMD_4 in the case where both the first and second bank select signals BANK_sel<0:1> are the high levels.
If the internal command signal CMD_internal is an active signal, one bank of the first to fourth banks 10 to 40 is activated. Also, if the internal command signal CMD_internal is a read signal or a write signal, one bank of the first to fourth banks 10 to 40 performs a read operation or a write operation.
Each of the first to fourth banks 10 to 40 may perform an operation according to the internal command signal CMD_internal. The temperature of a bank which operates more may be higher than the temperature of a bank which operates less.
If the temperatures of the respective banks vary, since the responding speeds of the respective banks change, the operation timings of the respective banks change, and thus, signals cannot help but be inputted to and outputted from the respective banks at different timings.
Therefore, if the output timings of the signals outputted from the respective banks change, a signal mismatch may occur in internal circuits, and this phenomenon may cause a mis-operation of a semiconductor memory apparatus.